Author(s) Details:
Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.
A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.
This section is a part of the chapter: Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate
XOR gate plays a vital role in most of the digital circuits and especially in most of the security algorithms (Babu and GA (2020). Nowadays the continuous growth of scaling of integration leads to the requirements of low-power, high-performance arithmetic circuits, which are predominantly used in portable devices and today’s advanced VLSI chip design (Weste and Harris (2011), Chandrakasan, Nikolić, and Rabaey (2003), especially applications like Artificial Intelligence and Internet of Things (IoT). Arithmetic circuits uncover abundant applications in processing architectures. As the complication of Digital signal processing architectures is relatively higher, low-power design techniques are now very promising (Kiran Kumar and Rai (2019). The performance parameters that influence the low power dissipation are governed by the fundamental power equation as shown in the following
How to Cite
Kommu, C., & Rani, A. D. (2025). Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, 1–14. https://doi.org/10.9734/bpi/stda/v5/2365